1. Field of the Invention
The present invention relates generally to a data processing system, and more particularly, to a data processing system executing a plurality of processings in a prescribed order using a plurality of processors.
2. Description of the Related Art
FIG. 11 is a block diagram showing the general configuration of a conventional data processing apparatus. The conventional data processing apparatus includes an MPU 20, an image input device 21, processing portions 22 to 25 to execute four processings, Log conversion, MTF correction, gamma correction and binarization, and an image output device 26.
Image input device 21 includes a photoelectric conversion element such as CCD, a driving system therefor, and an A/D converter, scans a document including both a continuous tone image and line drawing to generate a sampled analog signal, and quantizes the sampled analog signal using the A/D converter into data representing continuous tone reflectivity, in which each pixel has 8 bits (256 tones), for output as a digital signal.
Processing portion 22 performs Log conversion processing and calculates and outputs 8-bit continuous tone density data in the Log relation with the continuous tone reflectivity data output from image input device 21.
Processing portion 23 performs MTF correction processing. The MTF correction processing is performed to correct sharpness, and the sharpness of the 8-bit continuous tone density data obtained by the Log conversion at processing portion 22 is corrected using a digital filter such as Laplacian filter.
Processing portion 24 performs gamma correction processing. The gamma correction processing is performed to correct the difference in the tone curve between image input device 21 and image output device 26 so as to realize a desired gamma characteristic for the entire data processing apparatus. For example, using an LUT (Look Up Table) of 256 words, 8 bits, non-linear gamma correction data is output. The gamma correction processing may be also performed to set a desired gamma characteristic for the operator.
Processing portion 25 performs binarizing processing. The binarizing processing is performed to convert 8-bit continuous tone density data subjected to the gamma correction into 1-bit binary data corresponding to the brightness. The binarizing processing employs area-type tone binarizing such as error diffusion binarizing.
Image output device 26 is a printer such as an electrophotographic printer or ink jet printer, and prints the 1-bit binary data formed by binarization at processing portion 25 onto an output medium such as paper.
Image input device 21, processing portions 22 to 25 and image output device 26 are connected through an image data bus, and process data input in synchronization with a pixel clock common to them.
Thus, in the conventional data processing apparatus, image data input from image input device 21 is sequentially processed by processing portions 22 to 25 on a pixel data piece basis. In order to achieve synchronism in exchange of the pixel data among image input device 21, processing portions 22 to 25, and image output device 26, a pixel clock corresponding to each piece of pixel data is generated by a clock generator (not shown), and image input device 21, processing portions 22 to 25, and image output device 26 operate in synchronization with the pixel clock.
However, since the conventional data processing apparatus allows image input device 21, processing portions 22 to 25, and image output device 26 to operate in synchronization with a pixel clock, and the pixel clock must be generated based on any element having the lowest operating speed among image input device 21, processing portions 22 to 25, and image output device 26. As a result, the circuit must be constructed according to a processing portion forming a bottleneck, which makes difficult the circuit design.
In order to solve this problem, a circuit configuration in which image input device 21, processing portions 22 to 25 and image output device 26 are connected in an asynchronous manner so as to be operated in response to independent clocks may be considered. FIG. 12 is a block diagram for explaining a circuit configuration in which processing blocks are connected in an asynchronous manner. Referring to FIG. 12, processing blocks A, B and C can operate to perform processings in response to clock signals specific to them.
In this case, however, data cannot be directly exchanged among the processing blocks, and therefore buffer memories having a prescribed capacity should be provided among the blocks. Such a buffer memory can absorb the difference in the processing speeds of the processing blocks. Thus, if the processing blocks are connected in an asynchronous manner, a processing portion forming a bottleneck would not determine the processing speed of the data processing apparatus unlike the case of connecting image output device 21, processing portions 22 to 25 and image output device 26 as shown in FIG. 11 to operate in synchronization with one another. Meanwhile, the buffer memories are necessary, which pushes up the cost. In addition, since data is written/read to/from the buffer memory by two processing blocks, each block must accommodate such that one of the blocks can access a buffer memory, or such an arbitration processing must be performed by a controller provided for each of the buffer memories.
The present invention was made in view of the above, and it is one object of the present invention to provide a data processing system capable of processing data at a high speed. Another object of the present invention is to provide a data processing system which permits the memory capacity used to be reduced.
In order to achieve the above-described objects, a data processing system according to one aspect of the present invention includes a memory which stores a plurality of pieces of sequentially input data to be processed, a plurality of processors which execute a series of processings in a prescribed order to the data to be processed stored in the memory in the order of input, and a first controller which determines which processing is stagnant by monitoring the progress of a processing by each of said plurality of processors and prohibits a processor executing a processing succeeding to a processing determined as being stagnant from accessing the memory, and processings executed by the plurality of processors are executed asynchronously, and the plurality of processors share the memory.
More preferably, the system further includes a second controller to permit a processor executing a more preceding processing to access the memory if there are access requests from a plurality of processors to the memory at the same time.
According to the present invention, a data processing system capable of processing data at a high speed can be provided. Furthermore, a data processing system which permits data to be processed with a reduced memory capacity can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.